3D chip stacking is commonly used in recent commercialized products. Using vertical interconnection enabled by through Si via (TSV) technology in stacked chips, a significant improvement in bandwidth for the communications between the chips has been achieved. However, current chip stacking processes are mainly based on TSV technology, for which the issues of relatively large via dimension, alignment accuracy, and small via density remain unsolved. Monolithic 3-D integration has emerged as a promising technological solution for traditional transistor scaling limitations and interconnection bottleneck. The challenge we must overcome is a processing temperature limit for top side devices in order to ensure proper performance of bottom side devices. To solve this problem, we developed a low temperature III–V and Ge layer stacking process using wafer bonding and epitaxial lift-off, since these materials can be processed at a low temperature and provide extended opportunity/functionality (sensor, display, analog, RF, etc.) via heterogeneous integration. Therefore, we are exploring the monolithic 3D (M3D) integration of III–V and Ge materials and its applicability to CMOS, thin film photodiodes, mid-infrared photonics platforms, and MicroLED display integration for creating the ultimate 3-D chip of the future.

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